This invention relates to the manufacture of semiconductor devices, and more particularly to a method for making metal-gate MOS VLSI devices using metal silicide clading of source/drain regions.
In the manufacture of very high density MOS VLSI devices such as the 1-Megabit dynamic RAM, the electrical resistance of small-geometry elements has necessitated the use of metal gates and interconnects instead of polycrystalline silicon, and the use of silicide or "clad" source/drain regions. The processes used for creating a metal silicide in the surface of the source and drain regions often are not compatible with the metal gate, which must be in place when the clading is performed because self-alignment is necessary. For example, the etchant used to remove unreacted metal after the silicide is formed may etch the metal gate, or the silicide itself.
It is the principal object of the invention to provide an improved method of making metal-gate MOS VLSI devices, particularly high density memory cell arrays or the like. Another object is to provide a method of making an improved interconnect system and metal-gate transistor structure as may be used in very high density memory arrays. A further object is to provide an improved metal gate and clad silicon system with low sheet resistance and minimal process and materials complexity.